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copyright 1995 by dallas semiconductor corporation. all rights reserved. for important information regarding patents and other intellectual property rights, please refer to dallas semiconductor data books. ds1075 econoscillator/divider ds1075 101697 1/16 features ? dual fixed frequency outputs (200 khz 100 mhz) ? userprogrammable onchip dividers (from 1 513) ? userprogrammable onchip prescaler (1, 2, 4) ? no external components ? 0.5% initial tolerance ? 1% variation over temperature and voltage ? internal clock, external clock or crystal reference options ? single 5v supply ? powerdown mode ? synchronous output gating pin assignment 8 7 6 5 1 2 3 4 i/o out0 v cc gnd oscin xtal oe pdn /selx ds1075z 150mil soic ds1075m 300mil dip frequency options part no. max o/p freq. ds1075100 100 mhz ds107580 80 mhz ds107566 66 mhz ds107560 60 mhz description the ds1075 is a fixed frequency oscillator requiring no external components for operation. numerous operat- ing frequencies are possible in the range 0.2 to 100 mhz through the use of an onchip programmable prescaler and divider. the ds1075 features a master oscillator followed by a prescaler and then a programmable divider. the pres- caler and programmable divider are userprogram- mable with the desired values being stored in nonvola- tile memory. this allows the user to buy an off the shelf component and program it on site prior to board produc- tion. design changes can be readily accommodated by programming, or reprogramming, the desired values into the onchip nonvolatile registers. an evaluation board, ds1075k is available to simplify this task. the ds1075 is shipped from the factory configured for half the maximum operating frequency. prepro- grammed devices can be ordered on a custom basis as ds1075cxxx. as alternatives to the onboard oscilla- tor an external clock signal or a crystal may be used as a reference. the choice of reference source (internal or external) is userselectable at the time of programming (or on the fly if the sel mode is chosen). the ds1075 features a dualpurpose input/output pin. if the device is powered up in program mode this pin can be used to input serial data to the on chip registers. after a write command this data is stored in nonvolatile memory. when the chip is subsequently powered up in operating mode these values are automatically restored to the onchip registers and the input/output pin becomes the oscillator output. the ds1075 is available in 8pin dip or soic pack- ages, allowing the generation of a clock signal easily, economically and using minimal board area.
ds1075 101697 2/16 block diagram figure 1 internal oscillator en en en part no. suffix intosc frequency 100 80 66 60 100 mhz 80 mhz 66 mhz 60 mhz power on reset i/o cont. enabling sequencer pden en en rst m sel intclk extclk intosc en oscin xtal out0 output enable pdn /selx in/out sel en mclk m msel e/i en0 n div1 pdn 99 control logic signal path control path bus eeprom sel rst programmable divider n
ds1075 101697 3/16 pin descriptions input/output pin (in/out): this pin is the main oscilla- tor output, with a frequency determined by clock refer- ence, m and n dividers. except in programming mode this pin is always an output and will be referred to as aouto. in programming mode this pin will be referred to as aino. external oscillator input (oscin): this pin can be used to supply an external reference frequency to the device. crystal oscillator connection (xtal): a crystal can be connected between this pin and oscin to provide an alternative frequency reference. if a crystal is not used this pin should be left open. output enable function (oe pin): the ds1075 also features a asynchronouso output enable. when oe is at a high logic level the oscillator free runs. when this pin is taken low out is held low, immediately if out is already low, or at it's next hightolow transition if out is high. this prevents any possible truncation of the output pulse width when the enable is used. while the output is disabled the master oscillator continues to run (produc- ing an output at out0, if the en0 bit = 0) but the internal counters (/n) are reset. this results in a constant phase relationship between oe's return to a high level and the resulting out signal. when the enable is released out will make its first transition within one to two clock peri- ods of the master clock. powerdown/select function (pdn /selx pin): the powerdown/select (pdn /selx ) pin has a userse- lectable function determined by one bit (pdn bit) of the userprogrammable memory. according to which func- tion is selected, this pin will be referred to as pdn or selx . if the powerdown function is selected (pdn bit = 1) a low logic level on this pin can be used to make the device stop oscillating (active low) and go into a reduced power consumption state. the aenabling sequencero circuitry will first disable out in the same way as when oe is used. next out0 will be disabled in a similar fashion. finally the oscillator circuitry will be disabled. in this mode both outputs will go into a high impedance state. the power consumption in the powerdown state is much less than if oe is used because the internal oscil- lator (if used) is completely powered down. even if an external reference or a crystal is used all of the onchip buffers are powered down to minimize current drain. consequently the device will take considerably longer to recover (i.e., achieve stable oscillation) from a pow- erdown condition than if the oe is used. if the select function is chosen (pdn bit = 0) this pin can be used to switch between the internal oscillator and an external reference (or crystal) on the fly. when this mode is chosen the e/i select bit is overridden, a high logic level on selx will select the internal oscillator, a low logic level will select the external reference (or crys- tal oscillator). reference output (out0 pin): a reference output, out0, is also available from the output of the reference select mux. this output is especially useful as a buffered output of a crystal defined master frequency. out0 is unaffected by the oe pin, but is disabled in a glitchless fashion if the device is powered down. if this output is not required it can be permanently disabled by setting the en0 bit to one, and there will be a corresponding reduction in overall power consumption. userprogrammable registers the following registers can be programmed by the user to determine operating frequency and mode of opera- tion. details of how these registers are programmed can be found in a later section, in this section the function of the registers are described. the register settings are nonvolatile, the values being stored automatically in eeprom when the registers are programmed. note: the register bits cannot be used to make mode or frequency changes on the fly. changes can only be made by powering the device up in aprogrammingo mode. for them to be become effective the device must then be powered down and powered up again in aoperationo mode. for programming purposes the register bits are divided into two 9bit words, the amuxo word determines mode of operation and prescaler values. the adivo word sets the value of the programmable divider.
ds1075 101697 4/16 mux word figure 2 (msb) (lsb) 0* 0* 0* en0 pdn m msel div1 e/i * these bits must be set to zero e/i this bit selects either the internal oscillator or the exter- nal/crystal reference. 1=external/crystal 0=internal oscillator however, if the pdn bit is set to zero the e/i bit will be overridden by the logic level on the pdn /selx pin. table 1 pdn bit e/i pdn /selx pin oscillator mode 0 x 0 external/crystal 0 x 1 internal 1 x 0 powerdown 1 0 1 internal 1 1 1 external/crystal div1 this bit allows the master clock to be routed directly to the output (div1=1). the n programmable divider is bypassed so the programmed value of n is ignored. the frequency of the output (f out ) will be intclk or extclk depending on which reference has been selected. if the internal clock is selected the m prescaler is also bypassed (the bit values of msel and m are ignored) so in this case f out =intosc (which also equals mclk and intclk). if div1=0 the prescaler and programmable divider function normally. msel this bit determines whether or not the m prescaler is bypassed. msel =1 will bypass the prescaler. msel =0 will switch in the prescaler (unless overridden by div1=1), with a divideby number determined by the m bit. m this bit sets the divideby number for the prescaler. m=0 results in divideby4, m=1 results in divideby2. the setting of this bit is irrelevant if either div1=1 or msel =1. table 2 div1 bit e/i bit* msel bit m bit operation 0 0 0 0 internal oscillator divided by 4*n 0 0 0 1 internal oscillator divided by 2*n 0 0 1 x internal oscillator divided by n 0 1 x x external oscillator divided by n 1 0 x x internal oscillator divided by 1 1 1 x x external oscillator divided by 1 *assuming pdn bit = 1, otherwise internal/external selection will be controlled by the pdn /selx pin. div word figure 3 (msb) (lsb) n (9bits)
ds1075 101697 5/16 pdn this bit is used to determine the function of the pdn / selx pin. if pdn=0, the pdn /selx pin can be used to determine the timing reference (either the internal oscil- lator or an external reference/crystal). if pdn=1, the pdn /selx pin is used to put the device into power down mode. en0 this bit is used to determine whether the out0 pin is active or not. if en0 =1, out0 is disabled (highimped- ance). if en0 =0, the internal reference clock (mclk) is output from out0. the oe pin has no effect on out0, but out0 is disabled as part of the powerdown sequence. n these nine bits determine the value of the program- mable divider. the range of divisor values is from 2 to 513, and is equal to the programmed value of n plus 2: table 3 bit values divisor (n) value 000000000 000000001 . . . . . 111111111 2 3 . . . . . 513 note: the maximum value of n is constrained by the minimum output frequency. if the internal clock is selected, intosc/(m*n) must be greater than f outmin ; if the external clock is selected, extclk/n must be greater than f outmin . (if div1=1, then intosc or extclk, as applicable, must exceed f outmin ). operation of output enable since the output enable, internal master oscillator and/or external master oscillator are likely all asynchro- nous there is the possibility of timing difficulties in the application. to minimize these difficulties the ds1075 features an aenabling sequencero to produce predict- able results when the device is enabled and disabled. in particular the output gating is configured so that trun- cated output pulses can never be produced. enable timing the output enable function is produced by sampling the oe input with the output from the prescaler mux (mclk) and gating this with the output from the programmable divider. the exact behavior of the device is therefore dependent on the setup time (t su ) from a transition on the oe input to the rising edge of mclk. if the actual setup time is less than t suem then one more complete cycle of mclk will be required to complete the enable or disable operation (see diagrams). this is unlikely to be of any consequence in most applications, and then only if the value for n is small. in general, the output will make its first positive transition between approximately one and two clock periods of mclk after the rising edge of oe. figure 4 mclk t m t su t d t en oe out t m = period of mclk t d = prop delay from mclk to out max value of t en = t suem + 2 t m + t d min value of t en = t suem + t m + t d
ds1075 101697 6/16 disable timing if oe goes low while out is high, the output will be dis- abled on the completion of the output pulse. if out is low, the disabling behavior will be dependent on the setup time between the falling edge of oe and the rising edge of mclk. if t su < t suem the result will be one addi- tional pulse appearing on the output before disabling occurs. if the device is in dividebyone mode, the disabling occurs slightly differently. in this case if t su > t suem one additional output pulse will appear, if t su < t suem then two additional output pulses will appear. the following diagrams illustrate the timing in each of these cases. figure 5 mclk t m t su t outh t dis oe out t m = period of mclk t d = prop delay from mclk to out t outh = width of output pulse max value of t dis = t suem + t d + t outh min value of t dis = 0 n 2 t d figure 6 mclk t m t su t outh t dis oe out t m = period of mclk t d = prop delay from mclk to out t outh = width of output pulse max value of t dis = t suem + t d + t outh + t m min value of t dis = t suem + t d + t outh n = 1 t d select timing if the pdn bit is set to a0o, the pdn /selx pin can be used to switch between the internal oscillator and an external or crystal reference. the aenabling sequencero is again employed to ensure this transition occurs in a glitchfree fashion. two asynchronous clock signals are involved, intclk is the internal reference oscillator divided by one or whatever value of m is selected. extclk is the clock signal fed into the oscin pin, or the clock resulting from a crystal connected between oscin and xtal. the behavior of out0 is described in the following paragraphs, the out pin will behavior sim- ilarly but will be divided by n.
ds1075 101697 7/16 from internal to external clock this is accomplished by a high to low transition on the selx pin. this transition is detected on the falling edge of intclk. the output out0 will be held low for a mini- mum of half the period of intclk (t i /2), then if extclk is low it will be routed through to out0. if extclk is high the switching will not occur until extclk returns to a low level. figure 7 t low t i t sie selx out0 t e t i = period of internal clock t e = period of external clock depending on the relative timing of the selx signal and the internal clock, there may be up to one full cycle of t i on the output after the falling edge of selx . then, the alowo time (t low ) between output pulses will be depen- dent on the relative timing between t i and t e . the time interval between the falling edge of selx and the first rising edge of the externally derived clock is t sie . approximate maximum and minimum values of these parameters are: t low (min) = t i /2 t low (max) = t i /2 + t e t sie (min) = t i /2 t sie (max) = 3t i /2 + t e note: in each case there will be a small additional delay due to internal propagation delays. from external to internal clock this is accomplished by a low to high transition on the selx pin. in this case the switch is level triggered, to allow for the possibility of a clock signal not being pres- ent at oscin. note therefore, that if a constant high level signal is applied to oscin it will not be possible to switch over to the internal reference. (level triggering was not employed for the switch from internal to external reference as this approach is slower and the internal clock may be running at a much higher frequency than the maximum allowed external clock rate). when selx is high and a low level is sensed on extclk, out0 will be held low until a falling edge occurs on intclk, then the next rising edge of intclk will be routed through to out0. figure 8 t sei t e selx out0 t i t i = period of internal clock t e = period of external clock = t elow + t ehigh t low t ehigh t elow depending on the relative timing of the selx signal and the external clock, there may be up to one full t ehigh period on the output after the rising edge of selx . then, the alowo time (t low ) between output pulses will be dependent on the relative timing between t i and t e . the time interval between the falling edge of selx and the first rising edge of the externally derived clock is t sie . approximate maximum and minimum values of these parameters are:
ds1075 101697 8/16 t low (min) = t i /2 t low (max) = 3t i /2 + t elow t sei (min) = t i /2 t sei (max) = 3t i /2 + t ehigh note: in each case there will be a small additional delay due to internal propagation delays. powerdown control if the pdn bit is set to a1o, the pdn /selx pin can be used to powerdown the device. if pdn is high the device will run normally. powerdown if pdn is taken low a powerdown sequence is initiated. the aenabling sequencero is used to execute events in the following sequence: 1. disable out (same sequence as when oe is used) and reset n counters. 2. when out is low, switch out to highimpedance state. 3. disable mclk (and out0 if en0 bit = 0), switch out0 to high impedance state. 4. disable internal oscillator and oscin buffer. powerup when pdn is taken to a high level the following power up sequence occurs: 1. enable internal oscillator and/or oscin buffer. 2. set m and n to maximum values. 3. wait approximately 256 cycles of mclk for it to stabilize. 4. reset m and n to programmed values. 5. enable out0 (assuming en0 bit = 0). 6. enable out. steps 2 through 4 exist to allow the oscillator to stabilize before enabling the outputs. figure 9 pdn out out0 t stab t dis t pdn hiz hiz poweron reset when power is initially applied to the device supply pin, a poweron reset sequence is executed, similar to that which occurs when the device is restored from a power down condition. this sequence comprises two stages, first a conventional por to initialize all onchip circuitry, followed by a stabilization period to allow the oscillator to reach a stable frequency before enabling the outputs: 1. initialize internal circuitry. 2. enable internal oscillator and/or oscin buffer. 3. set m and n to maximum values. 4. wait approximately 256 cycles of mclk for the oscillator to stabilize. 5. load m and n programmed values from eeprom. 6. enable out0 (assuming en0=0). 7. enable out.
ds1075 101697 9/16 figure 10 v cc out out0 t por t stab programming normally when power is applied to the supply voltage pin the device will enter its normal operating mode fol- lowing the poweron reset sequence. however the device can be made to enter a programming mode if a pullup resistor is connected between in/out and the supply voltage pin, prior to powerup. the method used for programming is a variant of the 1wire tm protocol used on a number of dallas semiconductor products. hardware the hardware configuration is shown in the diagram. a bus master is used to read and write data to the ds1075's internal registers. the bus master may have either an opendrain or ttltype architecture. figure 11 bus master open drain port pin rx tx ds1075 1wire port 100 w mosfet rx tx data 5 m a typ. vdd 5k w rx = receive tx = transmit bus master ttlequivalent port pins rx tx to in/out of ds1075 5k w 5k w vdd a) open drain b) standard ttl programming mode is entered by simply powering up the ds1075 with a pullup of approximately 5k w . this will pull the in/out pin above v ih on powerup and initi- ate the programming mode, causing the ds1075 to internally release the in/out pin (after t por ), and allow the pullup resistor to pull the pin to the supply rail and await the master tx reset pulse (see diagram). note: to ensure normal operation any external pullup applied to in/out must be greater than 20k w in value. this will cause the in/out pin to remain below v ih on powerup, resulting in normal operation at the end of t stab .
ds1075 101697 10/16 figure 12 v cc program (pullup) oscillate (no pullup) t por in/out v oh v ih +5v +5v t por t stab first master tx reset pulse transaction sequence the sequence for accessing the ds1075 via the 1wire port is as follows: initialization function command transaction/data initialization all transactions on the 1wire bus begin with an initial- ization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the ds1075. the presence pulse lets the bus master know that the ds1075 is present and is ready to operate. figure 13 t rsth ds1075 master resistor master tx `reset pulse' ds1075 `presence pulse' t rstl t r t pdh t pdl 480 m s < t rstl < 960 m s 480 m s < t rsth < 960 m s 15 m s < t pdh < 60 m s 60 m s < t pdl < 240 m s v pullup v pullup min v ih min v il max 0v function commands once the bus master has detected a presence, it can issue one of the four function commands. all function commands are eight bits long, and are written lsb first. a list of these commands follows: write div register [01h] this command allows the bus master to write to the ds1075's div register. read div register [a1h] this command allows the bus master to read the ds1075's div register. write mux register [02h] this command allows the bus master to write to the ds1075's mux register. read mux register [a2h] this command allows the bus master to read the ds1075's mux register. transaction/data immediately following the function command, the nine data bits are written to or read from the ds1075. this data is written/read lsb first. the following diagrams illustrate the timing. once data transfer is complete a
ds1075 101697 11/16 new transaction sequence can be started by reinitializ- ing the device. therefore to program both the div and mux registers two complete transaction sequences are required. read/write time slots the definitions of write and read time slots are illustrated below. all time slots are initiated by the master driving the data line low. the falling edge of the data line syn- chronizes the ds1075 to the master by triggering a delay circuit in the ds1075. during write time slots, the delay circuit determines when the ds1075 will sample the data line. for a read data time slot, if a a0o is to be transmitted, the delay circuit determines how long the ds1075 will hold the data line low overriding the 1 gen- erated by the master. if the data bit is a a1o, the ds1075 will leave the read data time slot unchanged. write a1o time slot figure 14 t slot ds1075 master resistor ds1075 sampling window t low1 60 m s < t slot < 120 m s 1 m s < t low1 < 15 m s 1 m s < t rec < t rec 15 m s 60 m s v pullup v pullup min v ih min v il max 0v write a0o time slot figure 15 t slot ds1075 sampling window t low0 60 m s < t low0 < t slot < 120 m s 1 m s < t rec < t rec 15 m s 60 m s v pullup v pullup min v ih min v il max 0v
ds1075 101697 12/16 read data time slot figure 16 ds1075 master resistor t slot 60 m s < t slot < 120 m s 1 m s < t lowr < 15 m s 0 m s < t release < 45 m s 1 m s < t rec < t rdv = 15 m s t su < 1 m s v pullup v pullup min v ih min v il max 0v t rdv t release t lowr t su master sampling window return to normal operation when programming is complete the ds1075 should be powered down. if the pullup resistor on the in/out pin is removed, normal device operation will be restored next time power is applied. default register values unless ordered from the factory with specific register program values, the ds1075 is shipped with the follow- ing default register values: div = 0 0000 0000 (programmable divider will divide by two) mux = 0 0011 0100 out0 disabled powerdown enabled, select disabled m = 4 (ignored, see msel ) msel = 1 (m prescaler bypassed) div1 = 0 (n dividers enabled) e/i = 0 (internal oscillator selected)
ds1075 101697 13/16 absolute maximum ratings* voltage on any pin relative to ground 1.0v to +7.0v operating temperature 0 c to 70 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (t a = 0 c to 70 c, v cc = 5v + 5%) parameter symbol condition min typ max units notes supply voltage v cc 4.75 5 5.25 v highlevel output voltage (in/out, out0) v oh i oh = 4 ma, v cc = min 2.4 v lowlevel output voltage (in/out, out0) v ol i ol = 4 ma 0.4 v highlevel input voltage (pdn /selx , oe, in/out) (oscin) v ih v ih 2 3 v v lowlevel input voltage (pdn /selx , oe, in/out) (oscin) v il v il 0.8 2 v v highlevel input current (pdn /selx , oe, in/out) (oscin) i ih i ih v ih =2.4v, v cc = 5.25v v ih =v cc =5.25v 1 25 ua ua lowlevel input current (pdn /selx , oe, in/out) (oscin) i il i il v il =0,v cc =5.25v v il =0,v cc =5.25v 1 25 ua ua supply current (active) ds1075100 ds107580 ds107566 ds107560 i cc c l = 15 pf (both outputs) 35 50 ma standby current (powerdown) i ccq powerdown mode 0.8 ua
ds1075 101697 14/16 ac electrical characteristics (t a = 0 c to 70 c, v cc = 5v + 5%) parameter symbol condition min typ max units notes output frequency tolerance d f o v cc = 5v, t a = 25 c 0.5 0 +0.5 % combined freq. variation d f o over temp and voltage 1 +1 % long term stability d f o 0.5 +0.5 % maximum input f oscin external clock 50 mhz 1 maximum input frequency f oscin crystal reference 25 mhz 1 minimum output frequency f out 200 khz 2 powerup time t por + t stab 0.1 1 ms 3, 4 enable out from pdn t stab 0.1 1 ms 4 enable out0 from pdn t stab 0.1 1 ms 4, 5 out hiz from pdn t pdn 1 ms out0 hiz from pdn t pdn 1 ms load capacitance (in/out, out0) c l 15 pf 6 output duty cycle in/out out0 40 40 60 60 % % notes: 1. this is the maximum frequency which can be applied to oscin, or, the maximum crystal frequency that can be used. 2. the values of m, n and the frequency of oscin (if used) must be chosen so that this spec is met 3. this is the time from when v cc is applied until the output starts oscillating 4. when the device is initially powered up, or restored from the powerdown mode, oe should be asserted (high). otherwise the start of the t stab interval will be delayed until oe goes high. oe can subsequently be returned to a low level during the t stab interval to force out low after the t stab interval. if the external mode is selected t stab will be a function of the oscin period, i.e., external clock frequency. see acalculated parameterso to determine the value of t stab in this case. 5. although oe does not normally affect out0 operation, if oe is held low during powerup the start of the t stab period will be delayed until oe is asserted. if oe remains low, out0 will not start. 6. operation with higher capacitive loads is possible but may impair output voltage swing and maximum operation frequency.
ds1075 101697 15/16 ac electrical characteristics calculated parameters the following characteristic are derived from various device operating parameters (frequency, mode etc.). they are not specifically tested or guaranteed and may differ from the min and max limits shown by a small amount due to internal device setup times and propagation delays. however, these equations can be used to derive a more accurate idea of typical device performance than the guaranteed values. parameter symbol condition min max out from oe t en t m 2t m out from oe n = 1 n > 2 t dis t dis t outh 0 t outh + t m t outh selx to out0 internal to external external to internal t sie t sei t i /2 t i /2 3t i /2 + t e 3t i /2 + t ehigh break during sel switch internal to external external to internal t low t low t i /2 t i /2 t i /2 + t e 3t i /2 + t elow pdn to in/out hiz n = 1 n 2 t pdn t pdn t outh 0 t outh + t m t outh pdn to out0 hiz n = 1 n 2 t pdn t pdn t outh 0 t outh + t m t outh pdn to out t stab 256t m pdn to out0 t stab 256t m out after powerup 256t m out0 after powerup 256t m
ds1075 101697 16/16 data sheet revision summary the following represent the key differences between 11/16/97 and 05/01/97 version of the ds1075 data sheet. please review this summary carefully. 1. page 1, description, second paragraph. word change 2. page 14, ac electrical characteristic. add long term stability and new spec. the following represent the key differences between 05/01/97 and 10/15/97 version of the ds1075 data sheet. please review this summary carefully. 1. status change (remove preliminary).

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